#### floorplan
if { 1 } {
    set path [pwd]
    set date [exec date +%y%m%d]
    set topName DDR_ASYNC_LOGIC
    source /projects/cascade/workspace/xwqiu/DDRPHY/datain/scripts/proc.tcl
    source ${path}/flow/init.tcl
    source ${path}/flow/fp.tcl

    pr_check_row_R0

    source ${path}/flow/run_tcic.tcl
    source ${path}/scripts/add_pin.tcl
    source /projects/cascade/workspace/xwqiu/DDRPHY/datain/scripts/add_blkage.tcl

    loadIoFile ${path}/dataout/io.pin
 
    pr_check_inst
    # -> 128
    saveIoFile -locations ${path}/io.file

}

#### PG
if { 1 } {
    deleteInst WELLTAP*
    deleteInst ENDCAP*
    source ${path}/scripts/add_ENDCAP.tcl

    puts " add TAP CELL !!!"
    addWellTap -cell TAPCELLBWP240H11P57CPDSVT -cellInterval [expr 260*0.057] -inRowOffset [expr 40*0.057] -prefix WELLTAP -checkerBoard -fixedGap

    pr_connect_pg

    pr_t_add_pin_RouteBlkage "top" 15.1525 25.7925
    pr_t_add_pin_RouteBlkage "bottom" 13.2525 30.2765

    source /projects/cascade/workspace/xwqiu/DDRPHY/datain/scripts/add_PG.tcl
    pr_add_M0
    pr_add_M1ToM3

    ## PG color
    colorizePowerMesh -reverse_with_nondefault_width 1

    pr_t_add_via_RouteBlkage
    pr_add_M4ToM9
    pr_t_del_via_RouteBlkage
    pr_add_PG_VIA

    pr_check_inst
    # editPowerVia -add_vias 1 -top_layer M7 -bottom_layer M6 -area [lindex [dbget selected.box] 1] -nets {VDDC GNDC}
    saveDesign -tcon -abs ${path}/${topName}/PG.${date}

} 

#### place
if { 1 } {
    set path [pwd]
    set_dont_touch [get_cells -hierarchical *]
    set_dont_touch [get_nets -hierarchical *]
    
    setDesignMode -topRoutingLayer "M9"
    place_design
    optDesign -preCTS

    pr_report_timing
    timeDesign -preCTS -prefix place -outDir "./timeReport"

    pr_check_inst
    saveDesign -tcon -abs ${path}/${topName}/place.${date}

}

#### CTS
if { 1 } {
    source ./flow/ccopt.tcl
    optDesign -postCTS

    pr_report_timing
    timeDesign -postCTS -prefix CTS -outDir "./timeReport"

    pr_check_inst
    saveDesign -tcon -abs ${path}/${topName}/cts.${date}

}

#### route
if { 1 } {
    pr_t_del_pin_RouteBlkage
    routeDesign
    optDesign -postRoute

    pr_report_timing
    timeDesign -postRoute -prefix route -outDir "./timeReport"

    pr_check_inst
    saveDesign -tcon -abs ${path}/${topName}/route.${date}

}


#### fix short

verifyConnectivity
ecoRoute -fix_drc


#### output
source ${path}/scripts/get_hcell.tcl

source ${path}/flow/stream.tcl


#### eco

if { 0 } {
	ecoChangeCell -inst *** -cell ***
	ecoPlace
}